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发表于: 2018-5-15 16:22:30
| 显示全部楼层 |阅读模式
海信LED42K3110
Boot-
DRAM Channel A Calibration.
  0 00 00 ff ff

  1 00 00 ff ff

  2 00 00 ff ff

  3 00 00 ff ff

  4 00 00 ff ff

  5 00 00 00 ff

  6 00 00 00 ff

  7 00 00 00 00

  8 ff ff 00 00

  9 ff ff 00 00

10 ff ff 00 00

11 ff ff 00 00

12 ff ff 00 00

13 ff ff 00 00

14 ff ff 00 00

15 ff ff 00 00

16 ff ff 00 00

17 ff ff 00 00

18 ff ff 00 00

19 ff ff 00 00

20 ff ff 00 00

21 ff ff 00 00

22 ff ff 00 00

23 ff ff 00 00

24 ff ff 00 00

25 ff ff 00 00

26 ff ff 00 00

27 ff ff 00 00

28 ff ff 00 00

29 ff ff ff 00

30 ff ff ff ff

31 ff ff ff ff

32 ff ff ff ff

33 ff ff ff ff

34 ff ff ff ff

35 ff ff ff ff

36 ff ff ff ff

37 ff ff ff ff

38 ff ff ff ff

39 ff ff ff ff

40 ff ff ff ff

41 ff ff ff ff

42 ff ff ff ff

43 ff ff ff ff

44 ff ff ff ff

45 ff ff ff ff

46 ff ff ff ff

47 00 ff ff ff

48 00 ff ff ff

49 00 00 ff ff

50 00 00 ff ff

51 00 00 ff ff

52 00 00 ff ff

53 00 00 ff ff

54 00 00 ff ff

55 00 00 ff ff

56 00 00 ff ff

57 00 00 ff ff

58 00 00 ff ff

59 00 00 ff ff

60 00 00 ff ff

61 00 00 ff ff

62 00 00 ff ff

63 00 00 ff ff

64 00 00 ff ff

65 00 00 ff ff

66 00 00 ff ff

67 00 00 ff ff

68 00 00 ff ff

69 00 00 00 ff

70 00 00 00 ff

71 00 00 00 00

72 ff ff 00 00

73 ff ff 00 00

74 ff ff 00 00

75 ff ff 00 00

76 ff ff 00 00

77 ff ff 00 00

78 ff ff 00 00

79 ff ff 00 00

80 ff ff 00 00

81 ff ff 00 00

82 ff ff 00 00

83 ff ff 00 00

84 ff ff 00 00

85 ff ff 00 00

86 ff ff 00 00

87 ff ff 00 00

88 ff ff 00 00

89 ff ff 00 00

90 ff ff 00 00

91 ff ff 00 00

92 ff ff 00 00

93 ff ff ff 00

94 ff ff ff ff

95 ff ff ff ff

96 ff ff ff ff

97 ff ff ff ff

98 ff ff ff ff

99 ff ff ff ff

100 ff ff ff ff

101 ff ff ff ff

102 ff ff ff ff

103 ff ff ff ff

104 ff ff ff ff

105 ff ff ff ff

106 ff ff ff ff

107 ff ff ff ff

108 ff ff ff ff

109 ff ff ff ff

110 ff ff ff ff

111 00 ff ff ff

112 00 ff ff ff

113 00 00 ff ff

114 00 00 ff ff

115 00 00 ff ff

116 00 00 ff ff

117 00 00 ff ff

118 00 00 ff ff

119 00 00 ff ff

120 00 00 ff ff

121 00 00 ff ff

122 00 00 ff ff

123 00 00 ff ff

124 00 00 ff ff

125 00 00 ff ff

126 00 00 ff ff

127 00 00 ff ff

byte_i    status    best delay

0    3    8

1    3    8

2    3    29

3    3    30

========================================

1T = (86 - 19) = 67 delay cells
Clock frequency = 798 MHz, Clock period = 1253 ps, 1 delay cell =18 ps
Byte 0 : Gating(-33 ~ 33), Size=67 .
Byte 1 : Gating(-33 ~ 33), Size=67 .
Byte 2 : Gating(-33 ~ 33), Size=67 .
Byte 3 : Gating(-32 ~ 33), Size=66 .
error on bit 0 ,setup_time =hold_time =0!!
error on bit 1 ,setup_time =hold_time =0!!
error on bit 2 ,setup_time =hold_time =0!!
error on bit 3 ,setup_time =hold_time =0!!
error on bit 4 ,setup_time =hold_time =0!!
error on bit 5 ,setup_time =hold_time =0!!
error on bit 6 ,setup_time =hold_time =0!!
error on bit 7 ,setup_time =hold_time =0!!
error on bit 8 ,setup_time =hold_time =0!!
error on bit 9 ,setup_time =hold_time =0!!
error on bit 10 ,setup_time =hold_time =0!!
error on bit 11 ,setup_time =hold_time =0!!
error on bit 12 ,setup_time =hold_time =0!!
error on bit 13 ,setup_time =hold_time =0!!
error on bit 14 ,setup_time =hold_time =0!!
error on bit 15 ,setup_time =hold_time =0!!
HW Byte 0 : DQS(0 ~ 0), Size 0 , Set 0.
HW Byte 1 : DQS(0 ~ 0), Size 0 , Set 0.
HW Byte 2 : DQS(-8 ~ 16), Size 25 , Set 4.
HW Byte 3 : DQS(-10 ~ 15), Size 26 , Set 3.
RX DQ/DQS calibration fail!
DATLAT calibration
no DATLAT taps pass
default tx dq PI delay value(16) is fail on bit 0!!
default tx dq PI delay value(16) is fail on bit 1!!
default tx dq PI delay value(16) is fail on bit 2!!
default tx dq PI delay value(16) is fail on bit 3!!
default tx dq PI delay value(16) is fail on bit 4!!
default tx dq PI delay value(16) is fail on bit 5!!
default tx dq PI delay value(16) is fail on bit 6!!
default tx dq PI delay value(16) is fail on bit 7!!
default tx dq PI delay value(16) is fail on bit 8!!
default tx dq PI delay value(16) is fail on bit 9!!
default tx dq PI delay value(16) is fail on bit 11!!
default tx dq PI delay value(16) is fail on bit 12!!
default tx dq PI delay value(16) is fail on bit 13!!
TX HW Byte 0 : DQS(5 ~ -16), Size -20, Set 59.
TX HW Byte 1 : DQS(6 ~ -16), Size -21, Set 1.
TX HW Byte 2 : DQS(0 ~ 23), Size 24, Set 12.
TX HW Byte 3 : DQS(1 ~ 25), Size 25, Set 13.
TX DQ/DQS calibration fail!
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发表于: 2018-6-7 19:17:38
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刷程序试试。
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发表于: 2018-6-8 08:26:06
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查下DDR到主芯片排阻
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