上图的第三张简易座差错了,从新更换位置,线位也换了位置,打印信息终于出来了。但是ISP自动识别还是不能自动识别。
2018-4-13, 10:29:1
COM6, BaudRate:115200 bps, RXD: VGA->15,TXD: VGA->12, Printed by RT809F:
Boot-
DRAM Channel A Calibration.
1T = (80 - 18) = 62 delay cells
Clock frequency = 798 MHz, Clock period = 1253 ps, 1 delay cell =20 ps
Byte 0 : Gating(-31 ~ 32), Size=64 .
Byte 1 : Gating(-31 ~ 31), Size=63 .
Byte 2 : Gating(-31 ~ 31), Size=63 .
Byte 3 : Gating(-31 ~ 32), Size=64 .
HW Byte 0 : DQS(-9 ~ 15), Size 25 , Set 3.
HW Byte 1 : DQS(-11 ~ 12), Size 24 , Set 1.
HW Byte 2 : DQS(-9 ~ 14), Size 24 , Set 3.
HW Byte 3 : DQS(-11 ~ 14), Size 26 , Set 2.
DATLAT calibration
first_step= 11 total pass= 5 best_step=12 .
TX HW Byte 0 : DQS(1 ~ 26), Size 26, Set 13.
TX HW Byte 1 : DQS(2 ~ 27), Size 26, Set 15.
TX HW Byte 2 : DQS(2 ~ 24), Size 23, Set 13.
TX HW Byte 3 : DQS(1 ~ 24), Size 24, Set 13.
DRAM A Size = 768 Mbytes.
Boot
Start Pmain
0x0000a000
EMMC boot
CID:0xb8fa2221
:0x300296c9
:0x30344745
:0x11010030
LZHS addr:0x00100040
LZHS size:0x0015c118
LZHS checksum:0x000000e0
LZHS size:0x0015c118
store RSA & AES keys in DMX SRAM
LZHS begin
Boot
Start Lmain
MT5882 Boot Loader v0.9
Boot reason: A/C power on!!read from eeprom ioff 0 phy_off 3ee0
SIF_Master0: V2 design
IR DATA register : 0x 0
Boot reason: A/C power on!!T8032 init A/C on case loader stage...
Load T8032 FW (addr: 0x e31610, size: 23142)success!!
T8032 FW version: 6
T8032 change to loader stage...
LDR_FlashCopy 0xf010 0x62880 0x80
11010030:30344745:300296c9:11010030
id1:00303034 id2:47453002
eMMC Name: THGBMBG5D1KBAIL
Support network!1st MAC in EEP is valid (5c:36:b8:97:28:04)
1st : (5c:36:b8:97:28:04)
2nd : (ff:ff:ff:ff:ff:ff)
@@@@@@@@@epp_usbupgrade_flag[0x10]
Boot reason: A/C power on!!Boot reason: A/C power on!!
@@@@@@@@@rDtvCfg.u1Flags[16]@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@=
Org:0x10 Flags:0x10
cccccccccccccccccc
---------test LYQ check eeprom boot-----------
---------boot reason is not watchdog-----------
PDWNC_EnterPowerDown(100,0)
Disable VGA wakeup
Standby
PDWNC_MTK_SetupPowerDown breath!!SWITCH_T8032
?vEnterPowerStandby: Cbus_Init
shop finished and standby
H匔吤DRAM Channel A Calibration.
1T = (80 - 18) = 62 delay cells
Clock frequency = 798 MHz, Clock period = 1253 ps, 1 delay cell =20 ps
Byte 0 : Gating(-31 ~ 32), Size=64 .
Byte 1 : Gating(-31 ~ 31), Size=63 .
Byte 2 : Gating(-31 ~ 32), Size=64 .
Byte 3 : Gating(-31 ~ 31), Size=63 .
HW Byte 0 : DQS(-9 ~ 15), Size 25 , Set 3.
HW Byte 1 : DQS(-11 ~ 12), Size 24 , Set 1.
HW Byte 2 : DQS(-9 ~ 14), Size 24 , Set 3.
HW Byte 3 : DQS(-11 ~ 14), Size 26 , Set 2.
DATLAT calibration
first_step= 11 total pass= 5 best_step=12 .
TX HW Byte 0 : DQS(1 ~ 26), Size 26, Set 13.
TX HW Byte 1 : DQS(2 ~ 26), Size 25, Set 14.
TX HW Byte 2 : DQS(2 ~ 24), Size 23, Set 13.
TX HW Byte 3 : DQS(1 ~ 24), Size 24, Set 13.
DRAM A Size = 768 Mbytes.
Boot
Start Pmain
0x0000a000
EMMC boot
CID:0xb8fa2221
:0x300296c9
:0x30344745
:0x11010030
LZHS addr:0x00100040
LZHS size:0x0015c118
LZHS checksum:0x000000e0
LZHS size:0x0015c118
store RSA & AES keys in DMX SRAM
LZHS begin
Boot
Start Lmain
MT5882 Boot Loader v0.9
SIF_Master0: V2 design
IR DATA register : 0x 0
T8032 change to loader stage...
LDR_FlashCopy 0xf010 0x62880 0x80
11010030:30344745:300296c9:11010030
id1:00303034 id2:47453002
eMMC Name: THGBMBG5D1KBAIL
Support network!1st MAC in EEP is valid (5c:36:b8:97:28:04)
1st : (5c:36:b8:97:28:04)
2nd : (ff:ff:ff:ff:ff:ff)
@@@@@@@@@epp_usbupgrade_flag[0x10]
@@@@@@@@@rDtvCfg.u1Flags[16]@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@=
Org:0x10 Flags:0x10
cccccccccccccccccc
---------test LYQ check eeprom boot-----------
---------boot reason is not watchdog-----------
------[_LdrCheckEepromBoot] power mode = standby,ir or button wakeup---------
PDWNC_Init
Not support [LdrLedBlinkikng]!!
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